The tft lcm driver signals were enable signal and fiducial clock signal , which were strict with synchronization 驅(qū)動(dòng)信號(hào)主要為使能信號(hào)和基準(zhǔn)時(shí)鐘信號(hào),并要求二者具有嚴(yán)格的同步性。
Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper , carried on intact summing up to the data in the system , having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram , give solution that many pieces of sdram works togetherses of realizing heavy capacity , designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus , optimize back end state machine design and urge procedure making with lower , giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices , due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal , method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo 本文首先對(duì)數(shù)字減影血管造影( dsa )成像系統(tǒng)的組成結(jié)構(gòu)和數(shù)據(jù)流向進(jìn)行了深入研究和分析,并對(duì)系統(tǒng)中的數(shù)據(jù)流向進(jìn)行了完整的歸納和總結(jié),給出了x線數(shù)字成像系統(tǒng)中的高速大容量數(shù)據(jù)通道的設(shè)計(jì)方案;在對(duì)sdram的控制方式做了深入探討后,給出了實(shí)現(xiàn)大容量多條sdram共同工作的解決方案,在此基礎(chǔ)上設(shè)計(jì)了大容量幀存板實(shí)現(xiàn)對(duì)圖象數(shù)據(jù)進(jìn)行高速存儲(chǔ);通過對(duì)pci總線接口的深入研究,優(yōu)化后端狀態(tài)機(jī)設(shè)計(jì)和低層驅(qū)動(dòng)程序開發(fā),給出了完整的pci接口方案實(shí)現(xiàn)高速dma數(shù)據(jù)傳輸,完全可以滿足視頻傳輸要求;深入研究了基于大規(guī)??删幊唐骷臄?shù)字系統(tǒng)設(shè)計(jì)方法,針對(duì)通用fifo使能信號(hào)漂移、輸出數(shù)據(jù)難于建立和保持等設(shè)計(jì)難點(diǎn),提出了利用fpga中的鎖相環(huán)提供多個(gè)時(shí)鐘相移的信號(hào)來提高系統(tǒng)穩(wěn)定性的解決方案,從而實(shí)現(xiàn)利用fifo來協(xié)調(diào)系統(tǒng)各模塊之間的數(shù)據(jù)高速傳輸。